This invention relates generally to integrated latch or flip-flop circuits, and, more particularly, to a technique for correcting errors in the output signal of the latch due to single event upsets or on-chip coupling noise.
A single event upset (SEU) is the result of an ion transitioning through a semiconductor structure and, in doing so, causing charge to be deposited on critical circuit nodes within that structure. In a CMOS logic circuit, such as a latch circuit, this can cause an unintended switch in the output logic state, creating potentially catastrophic consequences for the system. In the case of storage cells and latch circuits, the primary SEU problem lies in the feedback path, where amplification and feedback of noise on a critical node can permanently change the cell's logic state.
Known SEU hardening or error-correcting techniques for CMOS logic include the use of redundant circuit paths, and for memory cells it is known to use cross-coupled resistors or capacitors. Multiple circuit paths provide redundancy and allow implementation of voting schemes to reduce the effect of SEUs. The addition of cross-coupled resistors and capacitors in a storage cell slows the cell's ability to latch false data. However, each of these techniques has its drawbacks. The typical voting scheme uses appended digital logic to recombine the redundant paths, which complicates clocking of sequential circuitry and may actually exacerbate the effects of the SEU. The addition of cross-coupled resistors and capacitors in a storage cell involves more complicated fabrication processes and results in slower response to all input signals, thereby decreasing its operating speed.
A need remains, therefore, for a robust latch circuit solution that substantially reduces errors due to SEUs or on-chip noise coupling.